Certain circuits require a plurality of voltage levels on a given conductor at various times for their operation. By way of example, there exists a type of integrated circuit known as Programmable Logic Devices (PLD's), which typically make use of one or more programmable interconnect arrays to configure themselves to a specific user's design. The programmable interconnect arrays are typically composed of nonvolatile, floating-gate memory cells (e.g., EPROM, EEPROM, flash EPROM, and the like).
Circuit features, including those of memory cells, grow ever smaller with improvements in integrated-circuit process technology. The reduction in feature size improves device performance while at the same time reducing cost and power consumption. Unfortunately, smaller feature sizes also increase a circuit's vulnerability to over-voltage conditions. Among the more sensitive elements in a modern integrated circuit are the gate oxide layers of the various MOS transistors. These layers are very thin in modern devices, and are consequently easily ruptured by excessive voltage levels. Modern circuits with small feature sizes therefore employ significantly lower source voltages than was common only a few years ago. For example, modern 0.18-micron processes employ supply voltages as low as 1.8 volts.
Floating-gate memory cells are erased using a physical effect known as “Fowler-Nordheim tunneling.” Such cells are programmed using either Fowler-Nordheim tunneling or another physical effect known as “hot-electron injection.” In either case, the required program and erase voltages are dictated by physical properties of the materials used to fabricate memory cells. Unfortunately, these physical properties have not allowed the voltages required to program, erase, and verify the program state of a memory cell to be reduced in proportion to reductions in supply voltages. For example, modern flash memory cells adapted for use with 0.18-micron processes require program and erase voltages as high as 14 volts, a level far exceeding the required supply voltage. Such memory cells are verified using a range of voltages from about zero volts to about 4.5 volts, the upper end of which is also potentially damaging to sensitive circuits.
The high voltages necessary to program, erase, and verify a memory cell can be provided from external sources or generated on chip. (As the term is used herein, “high-voltage” refers to voltage levels above the normal supply voltage VDD of the device.) On-chip generators typically include charge pumps that pump the supply voltage VDD to one or more desired high-voltage levels. The various voltages are then routed to the required destination circuits using one or more high-voltage power multiplexers.
Unfortunately, conventional on-chip voltage generators are very limited in terms of the power they can supply. First, the programming voltages are already on the upper end of what can be tolerated by modern semiconductor devices, making it difficult to increase power by stepping up the high-voltage levels. Second, increased output current generally comes at the expense of increased chip size. It is therefore desirable to maximize the output power of on-chip voltage generators without unduly increasing their size and power consumption.
FIG. 1 (prior art) depicts a conventional power multiplexer 100 that alternatively provides a high-voltage HV (e.g., 12 volts), a supply voltage VDD (e.g., 1.8 volts), or ground potential GND (e.g., zero volts) on an output terminal VOUT. High voltage HV is conventionally provided by a charge pump 105 controlled by a terminal enable-high-voltage pump EN_HVPMP, but can optionally be supplied from an off-chip source.
Multiplexer 100 includes a high-voltage switch 110, a VDD switch 115, a ground switch 120, and some select logic 125. In response to a pair of select terminals S1 and S2, select logic 125 closes one of switches 110, 115, and 120 as follows:                1. a logic one (e.g., VDD) on enable-high-voltage line EN_HV closes high-voltage switch 110 to provide voltage HV on terminal VOUT;        2. a logic one on enable-VDD line EN_VDD closes VDD switch 115 to provide supply voltage VDD on terminal VOUT; and        3. a logic one on enable-ground line EN_GND closes VDD switch 115 (by forward biasing an NMOS transistor 130) to provide supply voltage GND on terminal VOUT.        
Only one of enable signals EN_HV, EN_VDD, and EN_GND are logic one at any time. In general, both signals (e.g., signal EN_HV) and the corresponding physical node (e.g., lines or terminals) are referred to herein by the same name: whether a given reference pertains to a signal or a corresponding node will be clear from the context.
Multiplexers similar to multiplexer 100 are described in U.S. Pat. No. 5,650,672 entitled “High-Voltage Power Multiplexer” and U.S. Pat. No. 5,661,685 entitled “Programmable Logic Device with Configurable Power Supply,” both of which are incorporated herein by reference.
FIG. 2 (prior art) details an example of high-voltage switch 110 of FIG. 1, which includes a level shifter 200 having an output terminal connected to the gate of a high-voltage PMOS transistor 210. Level shifter 200 conventionally converts the zero-to-VDD logic signal on high-voltage enable line EN_HV into a zero-to-HV output signal on the gate of transistor 210. Setting high-voltage enable line EN_HV to a logic one makes transistor 210 conductive, which consequently provides high voltage HV on output terminal VOUT.
FIG. 3 (prior art) details a switch 115A, an example of switch 115 of FIG. 1, that includes a level shifter 300 having an output terminal connected to the gate of an NMOS transistor 310. Level shifter 300 conventionally converts the zero-to-VDD logic signal on enable line EN_VDD into a VT-to-V output signal on the gate of transistor 310, where V equals VDD plus the threshold voltage VT of NMOS transistor 310. The additional voltage VT compensates for the voltage drop from the gate of transistor 310 to output terminal VOUT so that switch 115A provides VDD on output terminal VOUT.
The trouble with switch 115A is two-fold. First, voltage V is above VDD, and is therefore generated using a charge pump or derived from charge-pump-generated voltage HV. As noted above, it is preferred to minimize the use of charge pumps. Second, transistor 310 is never entirely off because when enable line EN_VDD is zero, the gate voltage on transistor 310 is VT rather than zero. Thus biased, transistor 310 may shunt current from high-voltage line HV to output line VOUT. This current shunting wastes power and undesirably clamps high-voltage line HV to a voltage level below HV.
FIG. 4 (prior art) details a switch 115B, another example of switch 115, that addresses some of the shortcomings of switch 115A of FIG. 3. Switch 115B includes a pair of level shifters 400 and 405 having output terminals HLVLS connected to the gates of a pair of high-voltage PMOS transistors 410 and 415. An inverter 420 inverts VDD enable signal EN_VDD and provides the result to the control terminals CTRL of level shifters 400 and 405.
Level shifter 400 conventionally converts the zero-to-VDD logic signal from an inverter 420 into a zero-to-VDD output signal on the gate of transistor 410. Level shifter 405 converts the same zero-to-VDD logic signal from inverter 420 into an output signal on the gate of transistor 415 that ranges from zero volts to whatever the voltage level on output terminal VOUT. (Recall that the voltage on output terminal VOUT can be high-voltage HV or ground potential when VDD is de-selected).
Switch 115B overcomes both problems discussed above in connection with switch 115A. First, transistors 410 and 415 are PMOS transistors, so there is no VT drop between VDD and output terminal VOUT; second, when enable-VDD line EN_VDD is zero volts, transistors 410 and 415 are entirely off so there is no shunting of current from terminal VDD to line VOUT. Also, the configuration of transistors 410 and 415 ensures that each respective well is connected to the highest voltage applied to each transistor, which eliminates forward biasing of the PMOS transistor well. Unfortunately, these advantages are not without cost: the series resistance of the two transistors 410 and 415 limits the drive strength of switch 400.